PISCATAWAY, N.J.--(BUSINESS WIRE)--IEEE, the world's largest professional organization advancing technology for humanity, today announced that the IEEE Standards Association (IEEE-SA) Standards Board has approved IEEE 1800™-2012 “SystemVerilog—Unified Hardware Design, Specification and Verification Language.” The revised standard is intended to enhance and improve the efficiency of electronic-system design and verification.
“IEEE 1800 is intended to support productivity gains among design and verification engineers, and using this standard as a benchmark and the foundation for innovation will help industry deliver to consumers products that will surpass the capabilities of today’s solutions”
IEEE 1800-2012 is available immediately at no charge via the IEEE Get Program, which grants the public free access to view and download certain current individual standards. To view and download IEEE 1800-2012, please visit http://standards.ieee.org/about/get/index.html#get1800.
IEEE 1800 specifies SystemVerilog, the high-level design language used in the implementation and verification of electronic systems. The standard permits the use of a unified language for abstract and detailed specification of the design, specification of assertions, coverage and testbench verification based on manual or automatic methodologies. SystemVerilog offers application programming interfaces (APIs) for coverage and assertions, and a direct programming interface (DPI) to access proprietary functionality. SystemVerilog offers methods that allow designers to continue to use present design languages when necessary to leverage existing designs and intellectual property. Ultimately, IEEE 1800 is designed to help engineers reduce costly mistakes and improve time to market for in-demand products. In crafting IEEE 1800-2012, the third revision since the standard’s original publication in 2005, the members of the IEEE 1800 SystemVerilog Language Working Group collaborated to further refine the standard and gain consensus to make the necessary revisions.
“I would like to thank the global team of dedicated members who worked diligently to complete the standard,“ said Karen Pieper, chair of the IEEE 1800 SystemVerilog Language Working Group. “It is through their efforts and combined brain power, spirit of collaboration and tireless hard work that we complete this major revision. This revision shows a continued momentum for the standard as the go-to language to efficiently verify the ever-increasing complex IC and systems designs required by today’s electronics.”
The revised version of IEEE 1800, developed under the IEEE Computer Society’s Design Automation Standards Committee (DASC), encompasses more than 30 enhancements, notably the removal of the restriction to non-blocking assignments to class properties and the addition of multiple class interface inheritance. In addition, constraints can now be specified as “soft,” and typed new constructors can be used, facilitating fewer lines of self-documenting code.
“IEEE 1800 is intended to support productivity gains among design and verification engineers, and using this standard as a benchmark and the foundation for innovation will help industry deliver to consumers products that will surpass the capabilities of today’s solutions,” said Konstantinos Karachalios, managing director, IEEE-SA. “The spirit of collaboration behind IEEE 1800 and the free availability of the revised standard embody the concepts behind ‘OpenStand,’ a modern paradigm for global, open standards that the IEEE-SA supports as a model for improving the way that people around the world embrace and use technologies.”
For more information about the IEEE 1800 SystemVerilog Language Working Group, please visit http://standards.ieee.org/develop/wg/1800_WG.html.
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